1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the processes for forming field isolations or shallow trench isolation (STI).
2) Description of the Prior Art
The method of local oxidation of silicon(LOCOS) to form field oxide isolation around semiconductive devices built into the surface of silicon wafers has been practiced for over twenty-five years and has been adapted to many specific applications. In the process, a non-oxidizable mask of silicon nitride is formed over a thin layer of pad oxide grown on a blank silicon wafer. The mask is patterned by well known photolithographic methods and the wafer is oxidized, typically in steam, at temperatures in the neighborhood of 1,000.degree. C. The mask is patterned so that, after oxidation, mesa like regions of silicon are surrounded by a region of silicon oxide insulation. The semiconductive devices are then formed on the silicon mesas. Over the years many problems with LOCOS have surfaced which have been addressed in a great variety of ways. Most notable are the problems which deal with the growth of oxide under the mask(birds beak) and the resultant uneven surface topology over the field oxide.
A promising replacement for LOCOS field oxide isolation has been found in trench isolation. Although deep trench isolation(DTI) has been used nearly as long as LOCOS for bipolar transistor isolation, it has not been widely practiced in the manufacture of MOSFET integrated circuits. More recently, however, as device densities increase and isolation widths become smaller, shallow trench isolation(STI) is gaining favor over LOCOS in MOSFET technology.
The trenches are formed in the silicon around the semiconductor devices by reactive ion etching. They are then filled either entirely with silicon oxide or lined with silicon oxide and filled with another material such as polysilicon.
A major problem the inventor's have realized, as the scale of the devices shrinks, the width/area of the STI at the chip surface is to large, thus using up valuable active area. In addition, the isolation of logic device is not good enough at a feature size less than 0.18 .mu.m using conventional STI because the STI is too narrow below the wafer surface.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,688,044(Ohno) shows dope by I/I and isotropic etch.
U.S. Pat. No. 6,004,864(Huang et al.) show an isolation process. PA1 U.S. Pat. No. 5,629,226(Ohtsuki) shows a trench etch, dope and etch. PA1 U.S. Pat. No. 5,943,581(Lu et al.) shows an isotropic etch of a doped area to form a round trench. PA1 U.S. Pat. No. 6,020,250(Kenney) shows a process for horizontal trenches. PA1 U.S. Pat. No. 5,972,758(Liang) shows a STI trench. PA1 U.S. Pat. No. 5,112,771(Ishii et al.) shows a round STI trench. PA1 U.S. Pat. No. 5,432,365(Chin et al.) shows a shaped trench for a capacitor. PA1 U.S. Pat. No. 4,853,348(Tsuboushi et al.) shows a shaped trench for a capacitor.